Use component and process together vhdl

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I've been asked at the university to make a 4-bit bidirectional shift register. I did it first this way:

-- bidirektionale shift register mit data-load und serielle(R/L) output

library ieee;
use ieee.std_logic_1164.all;

entity bi_shift_reg is
    port( din: in std_logic_vector(3 downto 0);
            set, n_reset: in std_logic;
            sR, sL: in std_logic; -- Shift-Right/Shift-Left
            data_load: in std_logic;
            clk: in std_logic;
            dout: inout std_logic_vector(3 downto 0);
            s_dout_R: out std_logic; -- Serial Shift-Right output
            s_dout_L: out std_logic -- Serial Shift-Left output
            );
end bi_shift_reg;

architecture arch of bi_shift_reg is
begin
    
    process(clk,set,n_reset)
        begin
                -- reset (low aktiv)
                if n_reset = '0' then dout <= "0000";
                -- set
                elsif set = '1' then dout <= "1111";
                -- data-load
                elsif(rising_edge(clk) and data_load = '1') then 
                    s_dout_R <= din(0);
                    s_dout_L <= din(3);
                    dout <= din;
                -- shift right
                elsif(rising_edge(clk) and sR = '1') then
                    s_dout_R <= din(0);
                    dout(2 downto 0) <= dout(3 downto 1);
                -- shift left
                elsif(rising_edge(clk) and sL = '1') then
                    s_dout_L <= din(3);
                    dout(3 downto 1) <= dout(2 downto 0);
                end if;
        end process;

end arch;

but then I heard that I needed to use my previous coded D-Flipflop as a component for the shift register. So my question is: since I have new inputs (data_load,shift_left and shift_right) and outputs(Serial Shift-Right, Serial Shift-Left) how can I add them in my code along with the d-ff component? is it possible to use a component and process together ? This is my d-ff code with asynchronous activ-low reset and asynchronous set:

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop is
    port( d, clk, set, n_reset: in std_logic;
            q, qn: out std_logic
            );
end d_flipflop;

architecture arch of d_flipflop is
begin
    process(clk,set,n_reset)
    variable temp: std_logic; -- zwischenergebniss
    begin
         if n_reset = '0' then
            temp := '0';
         elsif set = '1' then
            temp := '1';
         elsif rising_edge(clk) then
            temp := d; 
         end if;
    q <= temp;
    qn <= not temp;
    end process;
end arch;

How can I use my flipflop to achieve the same result as the code for the shift-register ?

Thank you in advance for your answers :D

vhdl
1 Answers

After several good questions in the comment track by the OP, it is reasonable to post some design that can serve as an example for a solution.

Please note, that there was not any precise specification of the intended operation, e.g. what is priority between different inputs, and how should timing be for outputs, so the code below is provided with the intention of showing some VHDL structures that may works as a template for further update by the OP.

--###############################################################################
-- d_flipflop

library ieee;
use ieee.std_logic_1164.all;

entity d_flipflop is
  port(d, clk, set, n_reset : in  std_logic;
       q, qn                : out std_logic
       );
end d_flipflop;

architecture arch of d_flipflop is
begin
  process(clk, set, n_reset)
    variable temp : std_logic;          -- zwischenergebniss
  begin
    if n_reset = '0' then
      temp := '0';
    elsif set = '1' then
      temp := '1';
    elsif rising_edge(clk) then
      temp := d;
    end if;
    q  <= temp;
    qn <= not temp;
  end process;
end arch;


--###############################################################################
-- bi_shiftReg_ff

library ieee;
use ieee.std_logic_1164.all;

entity bi_shiftReg_ff is
  port(din          : in  std_logic_vector(3 downto 0);
       set, n_reset : in  std_logic;
       sR, sL       : in  std_logic;    -- Shift-Right/Shift-Left
       data_load    : in  std_logic;
       clk          : in  std_logic;
       dout         : out std_logic_vector(3 downto 0);
       s_dout_R     : out std_logic;    -- Shift-Right output
       s_dout_L     : out std_logic     -- Shift-Left output
       );
end bi_shiftReg_ff;

architecture arch of bi_shiftReg_ff is

  -- FF component
  component d_flipflop is
    port(d, clk, set, n_reset : in  std_logic;
         q, qn                : out std_logic
         );
  end component;

  -- FF data input
  signal d : std_logic_vector(3 downto 0);

  -- FF data output
  signal q  : std_logic_vector(3 downto 0);
  signal qn : std_logic_vector(3 downto 0);  -- Unused, but included for completness

begin

  -- Combinatorial process, thus making gates only
  process (all)
  begin
    -- data-load
    if (data_load = '1') then
      d <= din;
    -- shift right; priority over shift left
    elsif (sR = '1') then
      d <= '0' & q(q'left downto 1);  -- Discard right-most bit in the right shift
    -- shift left
    elsif (sL = '1') then
      d <= q(q'left - 1 downto 0) & '0';  -- Discard left-most bit in the left shift
    end if;
  end process;

  -- State held in FFs
  GEN_REG : for i in 0 to 3 generate
    REGX : d_flipflop port map
      (d(i), clk, set, n_reset, q(i), qn(i));
  end generate;

  -- Outputs drive
  dout <= q;
  s_dout_R <= q(q'right);  -- Bit 0, but shown with VHDL attributes
  s_dout_L <= q(q'left);   -- Bit 3, --||--

end arch;


--###############################################################################
-- EOF
user_23520820
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