What is the meaning of LLC-prefetch-misses perf event

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I'm trying to understand the meaning of the LLC-prefetch-misses perf event for Sandy Bridge.

From linux kernel source I see the definition of the event:

[ C(OP_PREFETCH) ] = {
    [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
    [ C(RESULT_MISS)   ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
},

where: SNB_DMND_PREFETCH = (SNB_PF_DATA_RD|SNB_PF_RFO) points to bits 4-5 of the event register, while SNB_L3_MISS = (SNB_DRAM_ANY|SNB_NON_DRAM) points to bits 22-36 of the event register.

Reading Intel® 64 and IA-32 Architectures Software Developer’s Manual, volume 3, chapter 18.3.4.5, I find that:

SNB_DMND_PREFETCH stand for the "Request_Type" and SNB_L3_MISS stand for the "Response_Type" fields of the MSR_OFFCORE_RSP_x Event Registers

Request:

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Response:

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However, I'm not able to understand the meaning of the "Response" in the context of prefetching.

Moreover, I found this definition in some courses slides:

Prefetch Hit: Prefetched line that was hit in the cache before being replaced (miss avoided)

Prefetch Miss: Prefetched line that was replaced before being accessed

Any suggestions regarding the meaning of LLC-prefetch and LLC-prefetch-misses events? Are the above definitions relevant?

Thank you.

perf prefetch caching linux
1 Answers

The event LLC-prefetch-misses occurs for an L2 hardware prefetch of any type (DATA_RD or RFO) where the target cache line was not supplied from a CPU cache. An L2 hardware prefetch is generated only when the target line doesn't exist in the same L2 cache in the required coherence state (E or M, for an RFO prefetch, or S, for a DATA_RD prefetch).

Processing a prefetch transaction may require snooping the private caches of other cores in the same NUMA domain or snooping caches in other NUMA domains. The SNB_DRAM_ANY flag in the event definition means that the event includes all snooping cases. The only two requirements for an event of type LLC-prefetch-misses is that it's an L2 hardware prefetch request and that the supplier is not a CPU cache. The supplier in this case is usually a local or remote DRAM controller.

The event LLC-prefetch is inclusive of LLC-prefetch-misses in the sense that it includes the cases where the supplier is a CPU data cache (L3, L2 , or L1D). An L2 prefetch that hits in the L3 is counted by LLC-prefetch but not by LLC-prefetch-misses. The LLC-prefetch count is at least as large LLC-prefetch-misses.

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