How to change the Makefile to create object file?

Question

I am following a code from GitHub (https://github.com/dmalhotra/pvfmm).

There is a Fortran file in ./examples/src/example-f.f90. I have created a subroutine from this example-f.f90 so that I can make an object file out of it and can call this subroutine in our in-house code. The installation guide is given here (https://github.com/dmalhotra/pvfmm/blob/develop/INSTALL).

The Makefile to compile the example-f.f90 is as (https://github.com/dmalhotra/pvfmm/blob/develop/examples/Makefile):

    ifndef PVFMM_DIR
    PVFMM_DIR=./..
    endif
    
    -include $(PVFMM_DIR)/MakeVariables
    
    ifndef CXX_PVFMM
    $(error Cannot find file: MakeVariables)
    endif
    
    # FC=$(FC_PVFMM) # TODO: for now, FC must be provided by user
    # CC=$(CC_PVFMM) # TODO: for now, CC must be provided by user
    CXX=$(CXX_PVFMM)
    CXXFLAGS=$(CXXFLAGS_PVFMM)
    LDLIBS=$(LDLIBS_PVFMM)
    
    RM = rm -f
    MKDIRS = mkdir -p
    
    BINDIR = ./bin
    SRCDIR = ./src
    OBJDIR = ./obj
    INCDIR = ./include
    
    TARGET_BIN = \
           $(BINDIR)/example1 \
           $(BINDIR)/example2 \
           $(BINDIR)/example-sctl \
           $(BINDIR)/fmm_pts \
           $(BINDIR)/fmm_cheb
    
    all : $(TARGET_BIN)
    
    $(BINDIR)/%: $(SRCDIR)/%.f90
        -@$(MKDIRS) $(dir $@)
        $(PVFMM_DIR)/libtool --mode=link --tag=FC $(FC) $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -o $@
...

The MakeVariables can be found in the above link.

I changed this make file so that I can make an object file of example-f.f90 (subroutine, I converted as I told before to link it in our in-house code) and also other files in our in-house code and link at the end. The new makefile looks like:

ifndef PVFMM_DIR
PVFMM_DIR=./..
endif

-include $(PVFMM_DIR)/MakeVariables

ifndef CXX_PVFMM
$(error Cannot find file: MakeVariables)
endif

FC_PVMM = mpif90
FC = mpif90

FC=$(FC_PVFMM) # TODO: for now, FC must be provided by user
CC=$(CC_PVFMM) # TODO: for now, CC must be provided by user
CXX=$(CXX_PVFMM)
CXXFLAGS=$(CXXFLAGS_PVFMM)
LDLIBS=$(LDLIBS_PVFMM)

RM = rm -f
MKDIRS = mkdir -p

BINDIR = ./bin
SRCDIR = ./src
OBJDIR = ./obj
INCDIR = ./include

all : $(project_final)

project_final: $(project)
    $(PVFMM_DIR)/libtool --mode=link --tag=FC mpif90 $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -o $@

project: example-f.o
    cd ./src && $(MAKE)

example-f.o: $(SRCDIR)/example-f.f90
    $(PVFMM_DIR)/libtool --mode=link --tag=FC mpif90 $(CXXFLAGS) -I$(INCDIR) $^ $(LDLIBS) -c $@
...

Kindly note 'project: example-f.o cd ./src && $(MAKE)' doing to make object files of our inhouse code. In src we have separate makefile to create object files for out in-house code.

But it gives me the following:

cd ./examples && make;
make[1]: Entering directory '/home/bidesh/Coding/FMM/pvfmm-1.3.0/examples'
make[1]: Nothing to be done for 'all'.
make[1]: Leaving directory '/home/bidesh/Coding/FMM/pvfmm-1.3.0/examples'

How can I modify the makefile so that I can compile the whole code that includes example-f.f90 (subroutine) along with other subroutines (in-house code)?

Thanks a lot.

How to change the Makefile to create object file?

0 Answers