I'm newish to C++ and GNU make, and I'm writing a C++ library. In the main directory I have is a Makefile that compiles the library into a shared object (.so). Then I have a subdirectory where I have some example programs using that library. These programs have separate Makefiles that first build the .so using the Makefile in the main directory, link the .so, and then compile the program.
The problem is there are variables in the main Makefile ($(CPP), $(FLAGS), $(CPPFLAGS), etc.) that are needed in the example Makefiles to compile the example programs. I could copy and paste the variables into each example Makefile, but this seems exhaustive and hard to track. One solution I've seen is to have a Makefile.defs file that defines all the relevant compilation variables which is then included by both the main Makefile and the example program Makefiles. Is this a good solution? Is there any problems with this? Are there any other solutions?