how does the diagram for this statement look like in multithreading

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I have come across this statement and I am wondering how it should be interpreted, please be patient with me thank you.

"Given a multi core system Pr1 and Pr2. The addresses Add1 and Add2 are mapped to the same cache block but A1 is not equal to A2. The cache state is initially invalid."

Would the cache blocks and processor look like the diagram I have drawn in A or in B? I'm confused about what it means when Add1 and Add2 are mapped to the same cache but does that mean that Pr1 and Pr2 access the same single block? Or do they each have their own blocks ?

My interpretation

I came across this diagram hence why I am confused how the architecture in this statement looks like.

architecture image

Any kind explanation is appreciated, thank you!

core cpu caching architecture multithreading
1 Answers

Think of a cache as a bounded hash table, as used by software. The addresses are hashed to the same location and that causes a collision.

  • A direct mapped cache maps to a array element (replacing on collision)
  • A set-associative cache will have a fixed sized list at the array slot (replacing the LRU within the list)
  • A fully-associative cache is a open addressed hash table (LRU across all elements).

In your example the cache starts out as empty (invalid blocks). When loading the memory location the two addresses map to the same cache line. If we assume direct mapped cache then the loads conflict, causing the other item to be evicted when loaded into the block. This conflict could be a performance problem by causing thrashing if both are hot entries being frequently used, thereby causing stalls due to memory fetches. An associative cache would support some collisions, e.g. 2-way might be enough in practice to avoid this problem in most cases. This might mean that a L1 direct mapped + 2-way L2 may be acceptable, where the per-core cache suffers from collisions but the shared cache does not and the penalty to main memory is avoided.

Ben_194500
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