As titled,
I've searched a lot of old articles on the Internet regarding memory data alignment, but I am not sure whether they are still useful nowadays. So, the question is regarding modern x86-64 CPUs, whether the memory data alignment is still beneficial for efficient data access? Or just an old convention adopted by all compilers for backward compatibility?
Yes for arrays because it means you'll avoid cache-line and page splits. See How can I accurately benchmark unaligned access speed on x86_64? for details on various penalties and how to measure them.
This is especially significant for vectorization with AVX-512, where looping over a misaligned array with 512-bit vectors means every load is a cache-line split. The penalty can be ~20%, vs. a few % with AVX 256-bit vectors on the same CPU even for data that's coming from L3 or DRAM, not L2 or L1d hits.
No for misalignment within a single cache line, for both integer and SIMD loads/stores on modern AMD and Intel microarchitectures. (Except for legacy-SSE where only aligned loads can be folded into a memory source operand like addps xmm0, [rdi] instead of separate movups. Unlike AVX where vaddps xmm0, xmm0, [rdi] doesn't require alignment.)
And yes potentially indirectly in terms of keeping all a struct's members in the same cache line, improving spatial locality.
