Using Parameters to declare variable-sized Vec

user_17183768 0
Viewed 90

I'm trying to have a variable-sized array based on a Module Paramete (example below). When the size PARAM is non-zero, the code works as intended.

class HWModule (PARAM : Int) extends Module{

    val my_Vec = RegInit(Vec(Seq.fill(PARAM)(0.U(32.W)))) 

    if (PARAM > 0){
        for (i <- 0 until PARAM -1){        
            my_Vec(i) := i.U //Example Code
        }     
    }
}

However, when I try to have PARAM = 0, it stops working. I've tried using Patter Matching (How do I write to a conditional output) to solve the problem, but I get the following error messages (and similar ones):

Equals does not take parameters

Expression does not convert to assignment because receiver is not assignable.

My goal is to be able to remove certain portions of code when PARAM = 0, while also allowing to variable-sized instantiation of Vecs, Regs, Wires, etc. If anyone could point me to a good solution or information about it, I would appreciate it.

Thank you, Miguel Silva

chisel
1 Answers

Maybe you can use Option like this :

val my_Vec_or_none = if(PARAM > 0) Some(RegInit(Vec(Seq.fill(PARAM))(0.U(32.W)))) else None

Then get register with get method :

    if (PARAM > 0){
        val my_Vec = my_Vec_or_none.get
        for (i <- 0 until PARAM -1){        
            my_Vec(i) := i.U //Example Code
        }     
    }

Also you can use indexed value directly (without intermediate val) :

val my_Vec = if(PARAM > 0) Some(RegInit(Vec(Seq.fill(PARAM))(0.U(32.W)))) else None

if (PARAM > 0){
    for (i <- 0 until PARAM -1){        
        my_Vec.get(i) := i.U //Example Code
    }     
}

And use this variable in another part of the code.

user_44229570
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