VHDL-2008 instantiation using hierarchical library path?

What do you call a VHDL instantiation that looks like this?:

  Osvvm.TbUtilPkg.CreateClock ( 
    Clk        => Clk, 
    Period     => Tperiod_Clk 
  ); 

Is this new to VHDL-2008? What are the rules to use this type of instantiation? It looks like they also relaxed the rules to allow anonymous instance names?

Here's the code I took the above snippet of code out of:

library ieee ;
  use ieee.std_logic_1164.all ;
  use ieee.numeric_std.all ;
  use ieee.numeric_std_unsigned.all ;

library osvvm ;
context osvvm.OsvvmContext ;
    
library osvvm_AXI4 ;
context osvvm_AXI4.AxiStreamContext ;
    
entity TbStream is
end entity TbStream ; 
architecture TestHarness of TbStream is

begin

  -- create Clock 
  Osvvm.TbUtilPkg.CreateClock ( 
    Clk        => Clk, 
    Period     => Tperiod_Clk 
  ); 
  
end entity;