SystemVerilog $bits() return type?

user_6883927 0
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As I know from SystemVerilog 3.1a Language Reference Manual "The $bits system function returns the number of bits required to hold an expression as a bit stream."

  1. What type this function returns?
  2. Is this type machine dependent maximum size?
  3. Is this maximum systemverilog type longint?

Any link to spec or docs revealing this mystery would be appreciated.

system-verilog
2 Answers

According to the System Verilog standard:

20.6.2 Expression size system function The $bits system function returns the number of bits required to hold an expression as a bit stream. The return type is integer

6.11 Integer data types integer -- 4-state data type, 32-bit signed integer

user_11438500

In terms of number of bits you can test in your simulator with a code like this

`define inspect(arg) \
  $display(`"arg = %b = %d (%0d bits)`", arg, arg, $bits(arg));

module bit_width;
  reg [4:0] x;
  reg [4'd4:4'd0] y;
  initial begin
    `inspect($bits(x));
    `inspect($bits(y));
  end
endmodule

In Icarus Verilog it prints

$bits(x) = 00000000000000000000000000000101 =          5 (32 bits)
$bits(y) = 00000000000000000000000000000101 =          5 (32 bits)

Suggesting that both will give 32 bits, fixed size.

To be honest, after reading your question, before testing, I would expect $bits(y) to have 4-bits.

user_127503530
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