Why does the device tree have to list interrupts for a UART device?

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On the device file tree listed here we can see an UART device:

uarta: serial@70006000 {
    compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
    reg = <0x0 0x70006000 0x0 0x40>;
    reg-shift = <2>;
    interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
    clocks = <&tegra_car TEGRA210_CLK_UARTA>;
    clock-names = "serial";
    resets = <&tegra_car 6>;
    reset-names = "serial";
    dmas = <&apbdma 8>, <&apbdma 8>;
    dma-names = "rx", "tx";
    status = "disabled";
};

The tegra210-uart driver is declared here

Why does uarta needs the interrupts section? Does it produce or receive interrupts? My guess is that it produces software interrupts: when it writes something to the serial, it triggers an interrupt. But why must this interrupt be listed in the device tree? And where is the code for this interrupt?

The second line of the above code block (reg = <0x0 0x70006000 0x0 0x40>) refers to an uart address. What is this address exactly? If I understand correctly, this is the address for a 8250_UART device but I'd like to know which pieces of this address do what, and how the kernel talks with this chip.

driver interrupt embedded-linux kernel linux
1 Answers

Driver documentation is available at https://www.kernel.org/doc/Documentation/devicetree/bindings/serial/nvidia%2Ctegra20-hsuart.txt

According to this forum https://forums.developer.nvidia.com/t/enabling-interrupts-for-uart-xavier-agx/166269 interrupts are used to prevent regular polling on UART.

Registering handler on this interrupt allows to only run code when effective data are received and available in DMA buffer, or when the complete outgoing message provided in DMA has been sent. Such a DMA usage example is available at: UART Tx mode with DMA enabled

Memory address 0x70006000 is the base location for UARTA controller registers (there are 4 UART [A,B,C,D] in Tegra 2) where to write commands or read status. These documents may help to understand:

For instance, the Scratch Register (SCR +0x07) can be used to write and read back any byte as a way to test UART is present and controller operates as expected.

I recommend you to download reference documentation, chapter 22 for UART, available from https://developer.nvidia.com/embedded/tegra-2-reference

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