How is uvm_component registered inside the uvm_factory?

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I've recently started studying the UVM and have some difficulty understanding the component/object registration process with the factory. Specifically, I can't find what line of code does the actual registration.

Here is my thought/search process:

  1. I've found that uvm_factory class has a register method which registers a proxy object of a given type

  2. This proxy object is of uvm_component_registry class parameterized with the type of the initially desired component/object

  3. Inside uvm_component_registry class there is a get method, which creates the proxy object me and registers it with the factory via factory.register(me) call

  4. In UVM Cookbook it says that every uvm_component should be registered with the factory by using the uvm_component_utils macro, which expands to the following code snippet:

    typedef uvm_component_registry #(T,`"S`") type_id;

static function type_id get_type();
  return type_id::get();
endfunction

virtual function uvm_object_wrapper get_object_type();
  return type_id::get();
endfunction

virtual function string get_type_name ();
  return type_name;
endfunction

So, here I come to the root of the problem. Inside the user class extended from the uvm_component class we have only the uvm_component_utils macro, which doesn't call the get method of the uvm_component_registry. Also there are no get method calls before the build phase during which we are creating the necessary class object using the factory. It certainly works, which means that our class has been registered. The question is - how? Are there some implicit get method calls?

uvm system-verilog
1 Answers

On the contrary, because the `uvm_component_utils macro adds

typedef uvm_component_registry #(T,`"S`") type_id;

That parameterized class has a static variable with a declaration initialization

local static this_type me = get();

This calls get() without ever having to construct the uvm_component_registry class because it is a specialization of the class. You might want to read my DVCon paper: Using Parameterized Classes and Factories: The Yin and Yang of Object-Oriented Verification, or watch my short course on SystemVerilog OOP for UVM Verification. The go into detail how the UVM implements the Factory Design Pattern in system-verilog

user_27556070
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