Can I provide macro/reference as parameter for hierarchical access in testbench? (SystemVerilog)

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I have some modules that I want to print some wires from in a PRINTER module. I have two different testbenches, which wraps these modules slightly differently, see code below. Is it possible to use the same PRINTER to print print_me_a and print_me_b using hierarchical references?

I know all the hierarchical references in the testbenches, and I know I could expand the PRINTER to instead take inputs and then connect relative references there, but hierarchical references inside the PRINTER are easier to expand if I want to add a lot of new prints, then I only have to change in the PRINTER.

Given the structure below I can't really utilize bind to make it work in both testbenches. I tried to instead of instance references use MOD_A.print_me_a and MOD_B.print_me_b, and that worked when I use VCS, but not in Questa, and I would like for the solution to work in both.

Is there any way to provide an hierarchical reference or name, or some macro, to the PRINTER as a parameter maybe, so that I can have the same code inside PRINTER for printing the wires in both testbenches? Or can I utilize some parameter which tells me which testbench the instance is used in to generate some different macros like `define MOD_A_DEF known_name_wrap_a.known_name_a for later common usage in PRINTER?

module MOD_A();
   wire print_me_a; // I want to print this
endmodule

module WRAP_A();
   MOD_A known_name_a();
endmodule

module MOD_B();
   wire print_me_b; // I want to print this
endmodule

module TOP_MOD();
   WRAP_A known_name_wrap_a();
   MOD_B known_name_b();
endmodule

module PRINTER();
   // Pseudo code, can I access these with hierarchical ref?
   $display(known_name_wrap_a.known_name_a.print_me_a)   // Only works in TOP_TB
   $display(known_name_a.print_me_a)                     // Only works in OTHER_TB
   $display(known_name_b.print_me_b);                    // Happens to work fine in both
endmodule

module TOP_TB();
   TOP_MOD top_mod();

   bind top_mod
   PRINTER top_tb_printer();
endmodule

module OTHER_TB();
   MOD_A known_name_a();
   MOD_B known_name_b();

   PRINTER other_tb_printer();
endmodule
system-verilog
1 Answers

You could use ports in your PRINTER module and connect them with relative hierarchical references.

module PRINTER(input wire a,b);
   initial $display(a);
   initial $display(b);
endmodule

module TOP_TB();
   TOP_MOD top_mod();

   bind top_mod PRINTER top_tb_printer(
       known_name_wrap_a.known_name_a.print_me_a,
       known_name_b.print_me_b
       );
endmodule

module OTHER_TB();
   MOD_A known_name_a();
   MOD_B known_name_b();

   PRINTER other_tb_printer(
       known_name_a.print_me_a
       known_name_b.print_me_b);
endmodule
user_27556070
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