VHDL AND multiple bit vector with a single bit

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Let's say I have a single bit std_vector called x, and 4 bit std_vector y. I want to AND all of the bits of y with x separately in a process. I know that I can do it in multiple lines like this:

output(3) <= y(3) and x;
output(2) <= y(2) and x;
output(1) <= y(1) and x;
output(0) <= y(0) and x;

But I want to do that in single line. How can I achieve it? Thanks.

1 Answers

You can create another signal where x is repeated as many times as needed, so that you can and it with the whole y vector at once.

signal xs : std_logic_vector(1 to y'length);

xs <= (others => x);
output <= y and xs;

I'm not sure if this can be reduced to a single line.

Or you can just write a loop:

for i in y'low to y'high loop
    output(i) <= y(i) and x;
end loop;
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