Why is import package outside module visible from other files/modules?

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  • file A
`timescale 1ns/10ps
import mypkg::*;
module test_A (
...
);
  • file B:
`timescale 1ns/10ps
module test_B (
...
);
  • Why are typedef of mypkg visible in file B? Isn't it supposed to be per compilation unit (=file here)?
system-verilog
1 Answers

Section 3.12.1 Compilation units of the IEEE 1800-2017 SystemVerilog LRM gives tools the choice of handling each file as a separate compilation unit like in C/C++, or every file being compiled on the command line as one compilation unit like in Verilog. All tools treat each file as a separate compilation unit if they are compiled with separate command lines.

Unfortunately there is no standard default choice; you need to read your tool's User Manual.

I know that Modelsim/Questa treats each SystemVerilog file as a separate compilation unit by default.

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