Is randomize an inbuilt function in SystemVerilog?

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class sample;
  randc bit[2:0]count;
endclass

module top;
  sample sample_test;
  initial begin
    sample_inst=new();
    repeat(20) begin
      sample_inst.randomize();
      sample.print();// this is assumed to be written in class
    end
  end
endmodule

I understood what rand and randc are, but I don't understand how we are able to use randomize() without writing a function in SystemVerilog class. I assume it is an inbuilt function. I have seen many codes online which don't have randomize function written in the class.

system-verilog
1 Answers

Yes, randomize is a built-in function, as defined in the IEEE Std 1800-2017, section 18.6.1 Randomize():

Variables in an object are randomized using the randomize() class method. Every class has a built-in randomize() virtual method, declared as follows:

virtual function int randomize();

This means that all the code examples you see online do not declare a randomize function.

Free copies of the IEEE Std are available. This should be your first source for all information.

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