Using existing Scala Class in new Class [Scala Chisel]

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This is probably a very basic question, but for the life of me I could not find an answer.

I have this existing logical AND class:

    class DelayedAND(val n:Int = 2) extends Module{
    val io = IO(new Bundle{
        val a = Input(UInt(1.W))
        val b = Input(UInt(1.W))
        val out = Output(UInt(1.W))
    })
     val delay = 2 
     val dand =io.a&io.b
     io.out := ShiftRegister(dand, delay)
    }

Which I need to include in this Class instead of a regular "and"

    class HalfAdder extends Module {
     val io = IO(new Bundle{
     val a    = Input(UInt(1.W))
     val b    = Input(UInt(1.W))
     val sum  = Output(UInt(1.W))
     val cout = Output(UInt(1.W))
     })
  
     val a_xor_b = io.a ^ io.b
     io.sum := a_xor_b

     val a_and_b = io.a & io.b  //previous Class needs to be used here
     io.cout := a_and_b
     }

I am completely new to Scala and Chisel and I already tried solving it for several hours! Please help me out, thanks!

chisel module scala class
1 Answers
val a_and_b = Module(new DelayedAND(2))
a_and_b.io.a  := io.a
a_and_b.io.b  := io.b
io.cout       := a_and_b.io.out

Here is a good explanation

https://www.chisel-lang.org/chisel3/docs/explanations/modules.html

Edit:

To give some more detail, a Module acts very similar to a typical Verilog module with the exception that clock and reset are implicitly inferred (there are exceptions which are listed in the link, and some others, but that's more indepth and beyond the scope of this question). In Chisel however, the Module represents what is to become a Verilog module after compilation/elaboration of Chisel to FIRRTL.

In a Verilog module we would list out ports and connect the ports via the port list in the module instantiation. The "ports" in this case are connected via the. := operator. This is assigning some logic to/from our Module "ports". If coming from a Verilog background, this can seem quite odd. Firstly, you can connect to the ports anywhere in the code! Effectively sprawling your "module instantiation" all over the place. If you're used to tracing signal connections in verilog for debug, this can seem a little daunting, however it has some benefits. You can modify what is connected to a particular port based on some parameter/variable. Nifty, suck it generate.

FIRRTL will complain if you don't connect one or more the Input's. Output's are fine to float/not connected, although you may see that some of your logic is optimized away depending on what is created.

So when first starting Chisel, take this approach of coding Module's much like you would a Verilog module. The more interesting features of Chisel will begin to surface as you try to figure out how to perform a certain hardware generation.

The benefits of Chisel come more from it's flexibility during complex systems more so than small examples, however understanding these small examples is key to progressing towards a mastery of the language.

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