Fetch - execute cycle for LMC instructions

user_15540037 0
Viewed 265

I have to define the steps for each Little Man Computer instruction (ADD, SUB, BR, BRP etc.), and I'm having trouble with the branching instructions and COB (or the Halt instruction). I understand the fetch portion where each instruction begins with:

PC -> MAR

MDR -> IR

But I'm unsure of what to add in the execute portion to make the instruction actually correct. Could anyone explain how to make the fetch-execute cycles for BR, BRP, BRZ and COB? Any help would be greatly appreciated

little-man-computer
1 Answers

First of all, the LMC is a virtual concept. It has several interpretations and implementations, which can sometimes be conflicting. So which answer is correct may depend on the course material you are working with.

To avoid confusion, here are the definitions we could use:

Registers and memory

  • MAILBOX: this is the memory outside of the processing unit. It has 100 entries for storing 3-digit numbers.
  • PC: Program Counter (two digits)
  • MAR: Memory Address Register: Temporarily holds the 2-digit address of a mailbox, used to fetch or store the value in the MDR.
  • MDR: Memory Data Register: Temporarily holds the 3-digit data being transferred to or from a mailbox.
  • IR: Instruction Register: includes opcode (1 or 3 digits) and sometimes a 2-digit address
  • ACC: Accumulator: a 3-digit value
  • N: Negative flag: is either on or off. This aspect is not well defined in the original LMC. Some simulators allow the ACC to hold negative values, and so no extra flag is needed, while other simulators will consider the ACC strictly limited to three digits only, with no support for a negative sign. As real CPUs typically have a N(egative) flag, I think it is reasonable to imagine this flag as a separate thing.
  • Z: Zero flag: is either on or off. This is an indication whether ACC has a zero value. Whether this should really exist as a separate flag is even more debatable than the N flag, but I just list it here as a possibility.

Fetch steps

The fetch part of the fetch-execution cycle is always the same -- I prefer to write assignments in the opposite direction:

  • MAR <= PC
  • MDR <= MAILBOX[MAR]
  • IR <= MDR
  • PC <= PC+1 (using calculator)

We could debate the exact order of the last step. The update of the PC could happen before or in parallel with steps 2 and 3.

Execution steps

The execution part of the fetch-execution cycle depends on the content of IR: the opcode (1 digit, or 901 or 902 for IN/OUT) is interpreted. For instance:

  • BR (also named BRA):

    PC <= IR(last 2 digits)

  • BRP:

    If N is not set:
          PC <= IR(last 2 digits)

  • BRZ:

    If Z flag is set:
          PC <= IR(last 2 digits)

  • COB:

    Program execution halts. No more fetch-execution cycle will follow until the external user triggers a run.

Depending on your course material, you may not be expected to mention the N or Z flags. In that case just replace the conditionals with "ACC is negative" and "ACC is zero" respectively.

Note that I didn't involve the MAR or MDR registers for these four instructions -- moving values from IR to PC directly -- as MAR and MDR are only needed for communication between the processing unit and memory.

user_54598390
Related