I have some problems with my VHDL file:
I want to multiply 14-Bit values. For this I just used the template provided in Quartus prime and modified it slightly.
Compiling my Code works fine, but if I try to simulate it with a .vwf file I always get the Error (vsim-3807).
Here is my code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity MultiplierAndCut is
port
(
a : in signed (13 downto 0);
b : in signed (13 downto 0);
clk : in std_logic;
clear : in std_logic;
result : out signed (27 downto 0)
);
end entity;
architecture rtl of MultiplierAndCut is
-- Declare I/O registers
signal a_reg, b_reg : signed (13 downto 0);
signal out_reg : signed (27 downto 0);
begin
process (clk, clear)
begin
if (clear = '1') then
-- Reset all register data to 0
a_reg <= (others => '0');
b_reg <= (others => '0');
out_reg <= (others => '0');
elsif (rising_edge(clk)) then
-- Store input and output values in registers
a_reg <= a;
b_reg <= b;
out_reg <= a_reg * b_reg;
end if;
end process;
-- Output multiplication result
result <= out_reg;
end rtl;
For my simulation I used a = [0 0 0 0 0 0 0 1 0 0 0 0 0 0] (should represent a decimal 1 in my system) and b = [0 0 0 0 0 0 0 0 0 1 0 0 0 0] (should represent a decimal 0.25)
My my simulation in the .vwf file looks as followed:
Thank you in advance for helping.