How to declare an array of arrays in the test bench of a VHDL code?

I have an array of arrays defined as the input to my entity. I used a package to define the array of arrays. In the test bench, I included that package and declared the component in the architecture but there is an error saying "formal port x does not exist in entity average. Please compare the definition of block average to its component declaration and its instantion to detect the mismatch." Attaching the declarations below. Please help.

-- the code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package vpkg is
    type m_array is array(1 downto 0, 1 downto 0) of std_logic_vector(7 downto 0);
end package;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.vpkg.all;

entity average is
    Port (x : in m_array;
          clk : in std_logic;
          y : out std_logic_vector(7 downto 0)  
     );
end average;

architecture avg_arch of average is
signal sum : std_logic_vector(8 downto 0) := (others => '0');
begin
process(x):
    for I in 0 to 1 loop
        for J in 0 to 1 loop
            sum <= sum + ('0' + x(I,J));
        end loop;
    end loop;
end process;
    y <= std_logic_vector(to_signed(to_integer(signed(sum) / 4),8));
end avg_arch;

--the test bench
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vpkg.all;

entity tb_average is
--      Port ( );
end tb_average;

architecture tb_average_arch of tb_average is

component average
    Port (x : in m_array;
          clk : in std_logic;
          y : out std_logic_vector(7 downto 0)  
          );
end component;

signal x : m_array;
signal clk : std_logic := '0';
signal y : std_logic_vector(7 downto 0);

begin
average_1 : average Port Map (x => x,clk => clk,y=>y);

input_proc : process
begin 
    wait for 100ns;
    x(0,0) <= "00001001";
    x(0,1) <= "00000110";
    x(1,0) <= "00000011";
    x(1,1) <= "00000001";
    wait; 
    
end process;

clk_proc : process
begin
    wait for 100ns;
    loop
        clk <= '1';
        wait for 10ns;
        clk <= '0';
        wait for 10ns;
    end loop;
end process;
    
end tb_average_arch;