How do you split modules into individual files using ChiselStage?

user_8834480 0
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I would like to split modules into files, like the old --split-modules flag used to do. Passing this flag to ChiselStage throws an error that this is deprecated, however I cannot find any documentation on what the supported arguments to ChiselStage are.

I am executing ChiselStage as follows:

object GenerateAsaSec extends App {
  val chiselStage = new ChiselStage
  chiselStage.execute(Array("-X", "verilog", "--split-modules", "--target-dir", "genrtl"), Seq(ChiselGeneratorAnnotation(() => new MyModule())))
}
chisel
1 Answers

Use -e or --emit-modules with a specific form you want to emit (chirrtl, high, middle, low, verilog, mverilog, or sverilog) to request that a specific emitter is run and splits all modules (or -E/--emit-circuit for an emitter that emits the circuit in one file).

The following should do what you want:

chiselStage.execute(
  Array(
    "-X", "verilog", 
    "-e", "verilog", 
    "--target-dir", "genrtl"), 
  Seq(ChiselGeneratorAnnotation(() => new MyModule()))
)

Tangentially, the error message there is worse than I thought. It should mention something about -e. Sorry about the confusion!

Anecdotally, the reason this was removed was that it was tricky to deal with a global option like --split-modules. Emitters are just transforms. It then became weird to have one global option that would affect all downstream transforms when a user might want a mix of file outputs produced by running a mix of transforms. E.g., the current version allows for emitting a high form circuit (-E high) and one-module-per-file Verilog (-e verilog) as arguments to the same invocation of ChiselStage.

user_38705490
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