How the mask can be used in aggregate memory in chisel?

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I'm tring to use aggregate memory in chisel.

As recommended in github, https://github.com/ucb-bar/chisel3-wiki/blob/master/Chisel-Memories.md

My code looks like follows:

class Interface(val w:Int) extends Bundle{
  val a: UInt = UInt(w.W)
  val b: UInt = UInt(w.W)
  val c: UInt = UInt(w.W)
}

val mem = Mem(16,new Interface(4))

Then I use mask as below:

mem.write(io.addr, inter, mask)

where the type of 'inter' is Interface, the type of 'mask' is Vec[Bool]

The following error is given:

Cannot prove that mytest.Interface <:< chisel3.Vec[_].

I have done some searching, found that mask can only be used when the memory is defined by Vec.

There is any solution to make this work?

chisel
1 Answers

As you noted, mask can only be used when the data type of the memory is a Vec.

You didn't describe how exactly you'd like the mask to correspond to the interface, but I'm assuming you would have a Vec of size 3, one bit for each a, b, and c.

The simplest solution is to just use Vec(3, UInt(4.W)):

val mem = Mem(16, Vec(3, UInt(4.W)))

If you then want to read and write as if it were actually made of Interface, you can cast:

mem.write(io.addr, inter.asTypeOf(Vec(3, UInt(4.W)), mask)

These casts are a little verbose, you can create type aliases to make the code more concise and maintainable:

val w = 4
val memType = Vec(3, UInt(w.W))
val intfType = new Interface(w)

val mem = Mem(16, memType)
mem.write(io.addr, inter.asTypeOf(memType), mask)

val read: Interface = mem.read(io.addr).asTypeOf(intfType)
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