Why DMB barrier is neceesary even though d-cache is disabled

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I was reading kernel source code (version, 5.9) and have a question in $(kernel_root)/arch/arm64/kernel/head.S.

There is a function SYM_FUNC_START_LOCAL(__create_page_tables) and some codes:

adr_l    x6, vabits_actual
str    x5, [x6]
dmb    sy
dc    ivac, x6

It reads supported VA_BITS from the running platform and store the value into vabits_actua. I undetstand the corresponding d-cache line has to be invalidated due to stale data that will affect unexpected behavior when d-cache is enabled later.

In this code, the order of the string code and d-cache line invalidating code is kept with DMB barrier instruction. However, I don't know why it's necessary.

My question is why the order has to be kept even though the d-cache is disabled.

arm64 memory-barriers assembly linux
1 Answers

As you can see from the function name (__create_page_tables) in the example, the MMU is disabled when this function was running. That means the cache and buffer are disabled as well. Therefore, it's not a problem of draining the buffer. That's because of the effect of DMB barrier instruction, prohibitting the re-ordering of the instructions.

Then, what if the order of DC instruction and store instruction are changed? Let's say there are two CPUs, A and B. The MMU of the A CPU is disabled but the MMU of the B CPU is enabled. If DC instruction executed before the store instruction due to re-ordering extension of ARM architecture, the MMU-enabled B CPU may fetch the invalidated data from the memory before the store instruction is finished. Then, that's an unexpected result. Therefore, the DMB barrier instruction necessary to make sure the MMU enabled CPU can have the synchronized data of the corresponding memory.

Reference: https://lore.kernel.org/kernelnewbies/CAEcHRToEjECSNpdocLwtd6M1vC2qEhBa2pziCV5g75d6h86kFQ@mail.gmail.com/T/#m390fd945500591ec444028da325b0d1481175be3

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