parameter based typedef in system Verilog

user_3303020 0
Viewed 1749

I would like to have parameterized typedef struct in System Verilog.

For example, Instead of separate definitions for 8 and 16 bits complex data, can I have parameterized typedef for complex data type?

typedef struct {logic [7:0] i, q;} complex_datatype_8b;
typedef struct {logic [15:0] i, q;} complex_datatype_16b;
register-transfer-level system-verilog verilog
2 Answers

There is no parameterized typedef construct, but you can have parameterized typedefs as a part of a parameterized module, interface, class, ...

module mod #(int A = 1, int B = 1)();
  typedef struct packed {logic [A-1:0] i, q;} t1;
  typedef struct packed {logic [B-1:0] i, q;} t2;
  ...
endmodule

A typical way to express parameterized typdefs in testbench is to use classes:

class cl #(parameter C = 1);
  typedef struct packed {logic [C-1:0] i, q;} tp;
endclass

module mod1();
  cl#(7)::tp t;
  ..
endmodule

Actually, you can use any parameters in place of constants in typedef.

user_11438500

Parametrized typedef is not possible but we need to do some tweaks to achieve similar results. Here we are using macros for it.

    `define MY_STRUCT_STAGE(NAME) \
       my_struct_t_``NAME``
     
    `define MY_STRUCT_STAGE_DEFINE(NAME, CNTR_TBL_ADDR_W, CNTR_TBL_DATA_W) \
     typedef struct { \
                     logic [CNTR_TBL_ADDR_W-1``:0] address; \
                     logic [CNTR_TBL_DATA_W-1:0] data; \
        } `MY_STRUCT_STAGE(NAME)

module module_struct #(parameter int ADDR = 3, parameter int DATA=2);
  `MY_STRUCT_STAGE_DEFINE(struct1,ADDR,DATA)
  `MY_STRUCT_STAGE(struct1)
endmodule

module top ();
  module_struct ms1(); // by default ADDR = 3 and DATA=2 with this structure is created
  module_struct #(5,6) ms2(); // struct is created with ADDR=5 and DATA=6
endmodule

I have taken reference from - https://verificationacademy.com/forums/systemverilog/parameterized-struct-systemverilog-design post

user_76058600
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