Let's say I have two modules M1 and M2 and both of them are outputting 32 bits data. I would like to do logic AND for each bit. How to do it? I have been looking into Library on GitHub but couldn't find module for AND operation.
I would like to do next:
X[0] = M1[0] && M2[0]
X[1] = M1[1] && M2[1]
etc.
Code example of add_gate:
@gear
async def and_gate(arg1, arg2) -> (Uint[32]):
async with arg1 as a1:
async with arg2 as a2:
res = a1 & a2
yield res
@alternative(and_gate)
@gear
async def and_gate_one_arg(args) -> (Uint[32]):
async with args as (a1, a2):
res = a1 & a2
yield res
res_two = []
res_one = []
@gear
def consumer():
arg1 = once(val=31, tout=Uint[32])
arg2 = once(val=15, tout=Uint[32])
args = once(val=(15, 31), tout=Tuple[Uint[32], Uint[32]])
bits_and_two_args = and_gate(arg1, arg2)
bits_and_one_arg = and_gate(args)
collect(bits_and_two_args, result=res_two)
collect(bits_and_one_arg, result=res_one)
consumer()
sim()
print(res_one)
print(res_two)
How it represents in GearBox:
