Dumping memory in a VCD file

user_14204617 0
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My main problem is that I can't have access to my inner signals while I'm using peek/poke testing. For example, I'm trying to debug a cache design and because of that, I want to see the content of the cache memory. As it's not IO, I can't expect it in my peekPokeTester file. I tried to dump it using the --memVCD flag, but it failed to recognize this flag.

Does anyone know how I can see the content or dump it in a VCD file?

chisel
2 Answers

If you are using the unit test framework chiseltest, if you use the verilator backend

import chiseltest.experimental.TestOptionBuilder._
...
test(new DUT).withFlags(Array("--t-use-verilator", "--t-write-vcd")) { dut =>

If you are using chisel iotesters use

iotesters.Driver.execute(
    Array("--backend-name", "verilator", "--generate-vcd-output", "on"),
    () => new DUT) { c =>

If you are using the lastest chisel release 3.4 then the default backend treadle can now log memories too.

Add the flags "--tr-mem-to-vcd", "<specifier>" where specifier is one of

  • "all" log all values at all locations of all memories
  • "mem1:all" log all values at all locations for memory mem1
  • "mem1:0-4" log values at locations 0-4 for memory mem1
  • "mem1:b0-b100" log values at locations 0-4 but show addresses in binary for memory mem1
  • "mem1:h0-hff" log values at locations 0-255 but show addresses in hex for memory mem1
  • "mem1:o0-o377" log values at locations 0-255 but show addresses in octal for memory mem1

If you are feeling really bold and your dut is not too large. You can take the generated firrtl of your dut and write a test directly in treadle which allows you to peek and poke just about everything. Here's some example code from the treadle's internal test suite.

user_3090390

If you are using chisel3, change the following in Chick's answer

import chiseltest.experimental.TestOptionBuilder._

to:

import chisel3.tester.experimental.TestOptionBuilder._

See further details can be found here.

user_148816860
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