What FPGA vendor boards are supported (well) by Chisel?

Chisel produces a synthesizable subset of Verilog 2001 that is supported by all FPGAs and FPGA tool vendors.

By example, you can write Chisel code for an inverter and use this to generate Verilog:

import chisel3._
import chisel3.stage.ChiselStage

class Inverter extends RawModule {
  val in = IO(Input(Bool()))
  val out = IO(Output(Bool()))
  
  out := !in
}

(new ChiselStage).emitVerilog(new Inverter)

The produced Verilog is shown here:

module Inverter(
  input   in,
  output  out
);
  assign out = ~in; // @[main.scala 10:10]
endmodule

This Verilog file can then be used in any FPGA toolchain (open or closed source) that supports Verilog. You would need to write the associated collateral that the toolchain wants (implementation constraints file, etc.). Functional verification can be done a lot of ways, e.g., writing Verilog/SystemVerilog testbenches for the generated Verilog, using cocotb for Python-based testbenches, or using one of the Chisel testing libraries (which actually run tests on the Verilog) like ChiselTest. ChiselTest actually uses Verilator as one of its possible backends meaning that the tests you write in ChiselTest will run on a Verilator-compiled binary. This is a concrete example of tight coupling between generated Verilog and a tool that only ingests Verilog.

Note: this views FPGA vendor tools as "Verilog to bitstream compilers" and not as "integrated development environments". By this view, FPGA vendor tools support any of the HDLs of a similar type including, but not limited to: Clash, nmigen, and SpinalHDL. For IDE-support, a Java IDE is going to be better for doing actual Chisel development, e.g., Emacs with Scala metals or IntelliJ Idea.

Chisel is not supported natively by any vendor tool that I know. The FPGA could be programed by open source compilers which could support natively chisel (I didn't find any, but that doesn't there is none).

Now it would still work well for FPGA design, the compiler will generate verilog that all the FPGA vendor tool supports. In that case, as you can see you are far from minimizing the gap between the simu and synthesis! But using chisel over low-level RTL language offers advantages that might overcome those differences in a lot of cases.

Since you are asking this question I am guessing that you don't have a lot of experience in FPGA. I would advice, to pick the same board as an open source project that uses chisel. This approach is true for any language you end-up picking (chisel or not), pick an open source of that language and take the same platform.

from the doc: https://www.chisel-lang.org/ " Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog."

major FPGA vendor tools:

Xilinx's vivado => check page 7, supports: VHDL, verilog, system verilog

Intel's quartus => page 54, supports: VHDL, verilog, system verilog

Mentors's questa => supports VHDL, Verilog, SystemVerilog, PSL, SystemC

open source compiler/ simulator:

Verilator supports: verilog, system verilog

yosys supports: Verilog-2005