Creating IO bundles using dynamic parameters in chisel using MixedVec

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My code is as follows

class HWBLOCK(dummy_val : Int)(p : Parameters) extends Bundle{
  private val temp = Reg(Vec(dummy_val, UInt(4.W)))
  def set_temp(Index : Int, my_val : Int){ temp(Index) := my_val.U}
  def get_temp(Index : Int) : UInt = { return temp(Index) }
  override def cloneType : this.type = (new HWBLOCK(stageNumber)(p)).asInstanceOf[this.type]
}

class MyMath(p : Parameters) extends Module{
  val para = p(MyBlockKey).para
  val io = IO(new Bundle{
    val myval = Input(MixedVec((1 until para) map {i => new HWBLOCK(i)(p)})) 
})

}

Now from the peekpoketester whenever I try this

poke(dut.io.myval(1).set_temp(1,1))

I get this error

overloaded method value poke with alternatives:
[error]   (signal: chisel3.Aggregate,value: IndexedSeq[BigInt])Unit <and>
[error]   (signal: chisel3.Bundle,map: Map[String,BigInt])Unit <and>
[error]   [T <: chisel3.Element](signal: T, value: Long)(implicit evidence$10: chisel3.iotesters.Pokeable[T])Unit <and>
[error]   [T <: chisel3.Element](signal: T, value: Int)(implicit evidence$9: chisel3.iotesters.Pokeable[T])Unit <and>
[error]   [T <: chisel3.Element](signal: T, value: BigInt)(implicit evidence$8: chisel3.iotesters.Pokeable[T])Unit <and>
[error]   (path: String,value: Long)Unit <and>
[error]   (path: String,value: Int)Unit <and>
[error]   (path: String,value: BigInt)Unit
[error]  cannot be applied to (Unit)
[error]         poke(dut.io.myval(1).set_temp(1,1))

Now I have 2 questions:

  1. Can I somehow avoid using private val inside HWBLOCK so that I don't have to use functions to set and get the values? The reason I am using private is because of this

The only caveat is if you are passing something of type Data as a "generator" parameter, in which case you should make it a private val. github.com/freechipsproject/chisel3/wiki/Bundles-and-Vecs

  1. If I have to use private is there a way I can use peekpoketesters to access the method inside HWBLOCK class.
1 Answers

The peek/poke testers in chisel-testers and chiseltest both treat modules as a black box and the only way to get data in and out is through the top level IO. It looks to me like you are trying to get around that restriction. I don't think there is an approach that is going to work. If you need to set some register in an internal hardware block you need to provide IO's to set and get it. If this is for one off diagnostic purposes you might consider using the BoringUtils to give access.

Is there a particular use case you are trying to solve by having a register inside a bundle? You should consider refactoring the HWBLOCK to be a module and use the power of scala to hook up the IO of each HWBLOCK in convenient fashion.

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