I try to initialize a clock system with HSE source, but the PLL is not getting ready (PLLRDY bit is not set), during debugging I figured out an infinite loop on that condition
while(!(RCC->CR & RCC_CR_PLLRDY));
but the code is actually good, my groupmate wrote it and checked. just in case write it below.
#include "stm32f4xx.h" // Device header
void MCO_Init(void);
int main(void)
{
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY;
RCC->CR |= RCC_CR_HSEON; //????? (8)
while(!(RCC->CR & RCC_CR_HSERDY));
RCC->CFGR &= ~RCC_CFGR_PPRE2_Msk;
RCC->CFGR |= 0b100 << RCC_CFGR_PPRE2_Pos; //APB2 AHB/2
RCC->CFGR &= ~RCC_CFGR_PPRE1_Msk;
RCC->CFGR |= 0b101 << RCC_CFGR_PPRE1_Pos; //APB1 AHB/4
RCC->PLLCFGR |= RCC_PLLCFGR_PLLSRC; //HSE —- PLL
RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLM_Msk;
RCC->PLLCFGR |= 8 << RCC_PLLCFGR_PLLM_Pos; // /8
RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLN_Msk;
RCC->PLLCFGR |= 336 << RCC_PLLCFGR_PLLN_Pos;// *336
RCC->PLLCFGR &= ~RCC_PLLCFGR_PLLQ_Msk;
RCC->PLLCFGR |= 2 << RCC_PLLCFGR_PLLQ_Pos; // /2 PLL = 168
RCC->CR |= RCC_CR_PLLON;
while(!(RCC->CR & RCC_CR_PLLRDY));
RCC->CFGR |= RCC_CFGR_SW_1;
RCC->CFGR &= ~RCC_CFGR_SW_0; // PLL —- AHB
while(!((RCC->CFGR & RCC_CFGR_SWS_1) && (RCC->CFGR |= RCC_CFGR_SW_0)));
RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; //Enable Clock for PORTD
GPIOD->MODER |= GPIO_MODER_MODE15_0; //Outpet Mode
GPIOD->OTYPER &=~ GPIO_OTYPER_OT15; //Push-Pull
GPIOD->OSPEEDR |= GPIO_OSPEEDR_OSPEED15_0; //Medium Speed
GPIOD->MODER |= GPIO_MODER_MODE13_0; //Output Mode
GPIOD->OTYPER &=~ GPIO_OTYPER_OT13; //Push-Pull
GPIOD->OSPEEDR |= GPIO_OSPEEDR_OSPEED13_0; //Medium Speed
while (1)
{
GPIOD->BSRR |= GPIO_BSRR_BS15;
for (int i = 0; i < 2000000; i ++);
GPIOD->BSRR |= GPIO_BSRR_BR15;
GPIOD->BSRR |= GPIO_BSRR_BS13;
for (int i = 0; i < 2000000; i ++);
GPIOD->BSRR |= GPIO_BSRR_BR13;
}
}
Could anyone help me to figure out how to fix it?((((