Artix-7 LUT usage too high for 6-input 1-output logic

user_1639049 0
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On Artix-7, one LUT is 6-bit input, 1-bit output. Presumably, any function I have with 6 bits input, 1 bit output I can implement by utilizing only one LUT.

When I synthesize the following code, however, I get a report saying 7 LUTs have been utilized. I am wondering why?

I am using Vivado 2019.2.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.numeric_std_unsigned.all;

entity test is
    port(
        d_in    : in std_logic_vector(5 downto 0);
        d_out   : out std_logic
    );
end entity test;

architecture RTL of test is
    
type t_int_array is array (natural range<>) of integer; 
constant primes : t_int_array(0 to 17) := (2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61);
    
begin
    
process(d_in)
begin
    
    d_out <= '0';
    for i in 0 to 17 loop
        if (d_in(5 downto 4) * d_in(3 downto 0) - d_in(0) = primes(i)) then
            d_out <= '1';
        end if;
    end loop;
    
end process;

end architecture RTL;

Here is the synthesized schematic.

Schematic

When I change the code to just skip one subtraction:

if (d_in(5 downto 4) * d_in(3 downto 0) = primes(i)) then
    d_out <= '1';
end if;

and synthesize, I get the expected 1 LUT utilized.

xilinx fpga vhdl
1 Answers

Vivado is probably really implementing some arithmetic from your first version. But it is partly your fault: you described all this as plain arithmetic while you wanted a constant look-up table. Why not computing your constant look-up table and then use it as is? The following is just an untested draft to show you an example of this functionally equivalent solution but significantly different on a pure synthesis point of view:

type lut6to1_t is array(0 to 63) of std_ulogic;
function is_prime_f return lut6to1_t is
  variable l: lut6to1_t := (others => '0');
  variable p: natural range 0 to 63;
begin
  for i in l'range loop
    p := ((i / 16) * (i mod 16) - (i mod 2)) mod 64;
    for j in primes'range loop
      if p = primes(j) then
        l(i) := '1';
      end if;
    end loop;
  end loop;
  return l;
end function is_prime_f;
constant is_prime: lut6to1_t := is_prime_f;

begin

  d_out <= is_prime(d_in);

end architecture rtl;

The main difference is that the synthesizer first computes the is_prime constant just like a simulator would do and then uses it to infers the hardware. A simple 6-to-1 LUT is thus sufficient instead of a uselessly complex arithmetic-based circuit.

Note that any other 64x1 constant, even arbitrarily complex to compute, would lead to the same resources usage after synthesis.

user_17737980
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