Suppose I want to load four consecutive aarch64 vector registers with values from consecutive memory locations. One way to do this is
ldp q0, q1, [x0]
ldp q2, q3, [x0, 32]
According to the ARM optimization guide for Cortex A72 (my target processor) each of these two instructions takes 6 cycles of execution time on the L-pipeline, for a total of 12 cycles.
But I can also use a load with interleaving, which allows me to load all 4 registers at once:
ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0]
This also saves me code size and should only need 8 cycles of execution time in total, acording to the above guide.
I know that interleaving means that the data is stored differently in my registers, but it should be assumed that my later use can handle both interleaved and non-interleaved data. (For example, summing an array.)
Is LD4 really faster than twice LDP here, as I read from the theoretical execution timings? The same question could of course also be asked for STP and ST4. Maybe there is anyone here who has already carried out benchmarks on this topic.
(And do I even interpret the timings correctly?)