How to use uint to do bit extraction

user_11580762 0
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I defined several varabiales, including post_addra, h_rdata and addra.

val post_addra=RegInit(0.U)
val addra=RegInit(0.U)
val h_rdata=RegInit(0.U)

Since post_addra is determined by h_rdata and addra. So I write this code.

post_addra := h_rdata(((addra+1.U) << 4.U)-1.U , (addra << 4.U) + 8.U)

However I got an error.

"[error] (x: BigInt,y: BigInt)chisel3.core.UInt

[error] (x: Int,y: Int)chisel3.core.UInt

[error] cannot be applied to (chisel3.core.UInt, chisel3.core.UInt)

[error] post_addra := h_rdata(((addra+1.U) << 4.U)-1.U , (addra << 4.U) + 8.U)"

The Chisel does not support using uint to extract. What should I do.

chisel scala
1 Answers

If I'm understanding correctly, it looks like you're trying to select a dynamic range of bits. I don't think you can do such dynamic selections (where even the width of the selected range is dynamic) using normal bit extract in Verilog, so I suspect the approach would be the same (can you express this in VHDL?).

In any case, bit extraction is isomorphic to right-shift and mask, so that's one way to solve this. You can dynamically right-shift by the lower bound, and then construct a mask of the correct width based on the difference between the lower and upper bounds:

val lower = (addra << 4.U) + 8.U
val upper = ((addra + 1.U) << 4.U) - 1.U
val mask = (1.U << (upper - lower)) - 1.U
post_addra := (h_rdata >> lower) & mask
user_24833290
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