Simple chisel dual port memory Read port issue

user_4623306 0
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I am trying to do the basic tutorial on chisel for verilog generation, I am trying to build a dual port memory:

import chisel3._
import chisel3.stage.ChiselStage

class Memo extends Module {
  val io = IO(new Bundle {
    val wen     = Input(Bool())
    val wrAddr  = Input(UInt(8.W))
    val wrData  = Input(UInt(8.W))
    val ren     = Input(Bool())
    val rdAddr  = Input(UInt(8.W))
    val rdData  = Output(UInt(8.W))
  })

  val mem = Mem(256, UInt(8.W))

  when(io.wen) {
    mem(io.wrAddr) := io.wrData
  }

  io.rdData := 0.U
  when(io.ren) {
    io.rdData := mem(io.rdAddr)
  }

}
println((new ChiselStage).emitVerilog(new Memo))

The above code compiles without issues. But I want to hold the rdData value to the old value if ren = 0. For that I commented line io.rdData := 0.U and I got the error:

 Errors: 1: in the following tutorials
    Tutorial Memo: exception  @[:@6.4] : [module Memo]  Reference io is not fully initialized.
      @[Memo.scala 31:15:@15.6] : io.rdData <= mux(io.ren, mem._T_20.data, VOID) @[Memo.scala 31:15:@15.6]

How do I fix this? How to hold the previous value on rdData? Also what does the Error message mean, that io is not initialized?

chisel
1 Answers

The uninitialized error means there are possible simulation paths where the wire io.rdData had never been assigned. If you need to hold onto some value I'd suggest adding a register, something like this.

val mem = Mem(256, UInt(8.W))

  when(io.wen) {
    mem(io.wrAddr) := io.wrData
  }

  val lastValue = RegInit(0.U(8.W))

  io.rdData := 0.U
  when(io.ren) {
    io.rdData := mem(io.rdAddr)
    lastValue := io.rdData
  }.otherwise {
    io.rdData := lastValue
  }
user_3090390
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