VHDL 8-bit adder with carry & testbench

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Heyo! I've been trying to get into programming vhdl again for some upcoming classes and tried to do an simple 8-bit adder and wanted to test it with a testbench. (I'm working with the Vivado Xilinx Software btw~)


I don't get any syntax errors, but it shows the variables as "U" (I guess undefined?) Hope it's easy to see what I did (and why lol). Yea but I can't really find the problem??

My code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity addierer is
    Port ( a : in STD_LOGIC_VECTOR(7 downto 0);
           b : in STD_LOGIC_VECTOR(7 downto 0);
           cin : in STD_LOGIC;
           s : out STD_LOGIC_VECTOR(7 downto 0);
           cout : out STD_LOGIC);
end addierer;

architecture Behavioral of addierer is


COMPONENT volladdierer is
    Port ( a    : in STD_LOGIC;
           b    : in STD_LOGIC;
           cin  : in STD_LOGIC;
           s    : out STD_LOGIC;
           cout : out STD_LOGIC
           );
end COMPONENT;

signal c : STD_LOGIC_VECTOR(6 downto 0);

begin

    PROCESS (a,b,cin)
    BEGIN

    s(0) <= a(0) xor b(0) xor cin; --erstes s wird noch mit cin berechnet
    c(0) <= (cin and b(0)) or (cin and a(0)) or (a(0) and b(0)); --sowie das erste cout

    for i in 1 to 7 loop --Schleife um Stellen der Arrays durchzugehen

        s(i)    <= a(i) xor b(i) xor c(i-1);
        c(i)      <= (c(i-1) and b(i)) or (c(i-1) and a(i)) or (a(i) and b(i));    

    end loop;

    cout <= c(6);

    END PROCESS;

end Behavioral;

testbench I used:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


entity testbench_addierer is
--  Port ( );
end testbench_addierer;

architecture Behavioral of testbench_addierer is


                SIGNAL a    : STD_LOGIC_VECTOR(7 downto 0);
                SIGNAL b    : STD_LOGIC_VECTOR(7 downto 0);
                SIGNAL cin  : STD_LOGIC;
                SIGNAL s    : STD_LOGIC_VECTOR(7 downto 0);
                SIGNAL cout : STD_LOGIC;

                COMPONENT addierer IS
                    PORT(
                            a   : IN STD_LOGIC_VECTOR(7 downto 0);
                            b   : IN STD_LOGIC_VECTOR(7 downto 0);
                            cin : IN STD_LOGIC;
                            s   : OUT STD_LOGIC_VECTOR(7 downto 0);
                            cout: OUT STD_LOGIC
                        );
                END COMPONENT;




begin

U1: addierer
PORT MAP( 
        a => a,
        b => b,
        cin => cin,
        s => s,
        cout => cout
        ); 



    process
        begin


            a <= "00000000" after 0ms;
            a <= "00000001" after 10ms;
            a <= "01010101" after 20ms;

            b <= "00000000" after 0ms;
            b <= "10001001" after 10ms;
            b <= "00000001" after 20ms;

            cin <= '0' after 0ms;
            cin <= '0' after 10ms;
            cin <= '0' after 20ms;



    end process;
end Behavioral;

Thanks already and hmu if something's unclear in my code!! (and pls keep in mind I'm an total beginner.. xD)

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