While executing mret instruction while returning from an interrupt, the very next write operation CPU does causing an exception with excode as 7 (store access fault).
Then mstats.MPP value changes to 00 (user mode). Though, processor previously was into machine mode. This is fine as per RISCV specs. I've configured interrupt into CLIC vectored mode.
I cannot find a reason why CPU land into the exception. But, If I forcibly change the value of mstatus.MPP to machine before doing any write operation, things work just fine. There is no exception with this case. This behavior is an unexpected.
I'll appreciate some pointers to fix this issue!!