Creating a Wire with a custom index range

Is it possible to create a Wire in Chisel3 with custom indexing like how it's done in Verilog?

Here's an example of how it can be done in Verilog:

wire [7:4] a;

I have tried to create an equivalent Chisel3 code with Input wire having custom range as shown in the following code :

class cl extends Module{
    val io=IO(new Bundle{
        val in = Input(UInt(range = (7,4)))
        val out = Output(UInt(4.W))
    })
    io.out := io.in
}

However I get the following error during compilation :

[error] (range: (chisel3.internal.firrtl.NumericBound[Int], chisel3.internal.firrtl.NumericBound[Int]))chisel3.core.UInt
[error] (range: chisel3.internal.firrtl.Range)chisel3.core.UInt
[error] cannot be applied to (range: (Int, Int))
[error] val in = Input(UInt(range=(7,4)))

Is there a valid syntax for Chisel3 to create a Wire with custom indexing like how it is shown in the Verilog example?