Cortex M - Atomicity of IRQ disabling

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I've spent hours trying to answer my question, but could not find any satisfying answer.

Since ARM Cortex-M cores does not have any instruction to read the state of global interupt mask (PRIMASK register) and immediately disabling it, all frameworks are using the following sequence of two instructions:

mrs r0, PRIMASK ; Read current state
cpsid i         ; Mask IRQs

But there is no explanation, why this piece of code is considered atomic... What happens when the IRQ comes in between the execution of this two instructions and the IRQ handler changes the state of PRIMASK? Like

mrs r0, PRIMASK ; Read current state
; Some weird IRQ handling happens here and changes PRIMASK
cpsid i         ; Mask IRQs

Since this code is widely used, I suspect that this situation should never happen by (architecture?) design. Could somebody please explain to me why? :-) Thanks!

cortex-m arm atomic assembly
1 Answers

What happens when the IRQ comes in between the execution of this two instructions and the IRQ handler changes the state of PRIMASK?

The program will randomly lock up, as this would also break most other "wait for interrupt" methods (like volatile variables).

Remember that an interrupt can only occur if it is not masked, so the interrupt handler could only ever disable interrupts. But disabling interrupts globally will also prevent other interrupts from fireing - and the code waiting for some hardware interaction usually does not re-enable interrups randomly.

That is why an interrupt handler is considered br0ken when it modifies PRIMASK or FAULTMASKwithout restoring it on exception return.

user_4108470
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