In VHDL, is there a limit to how many ANDs and ORs one can have in an if statement?

If I have slv_flag(11 downto 0) and others, is there a limit to the number of ANDs and ORs?

If slv_flag(1) = '1' and slv_this(3) = '0' and slv_that(7) = '1' and int_count > 353 then
     slv_action <= "10101010";
end if;


If (slv_flag(1) = '1' and slv_flag(3) = '0' and slv_flag(7) = '1' and slv_flag(12) = '0') or slv_flag(0) = '1' then
         slv_action <= "10101011";
    end if;