How the RISC-V processor detect modes when handling exceptions?

user_12101193 0
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I've read riscv-privileged manual and known if an interrupt or exception happen, the current mode will be saved in xPP (x maybe M or S).

But I found it difficult to understand these xpp bits in xstatus. xPP records the previous mode, but where is the current mode stored?

Also, I think this manual is brief but lacking examples.. https://riscv.org/specifications/privileged-isa/

Is there a recommended extra manuals for learning?

riscv
1 Answers

I think this will depend on your specific risc-v implementation. E.g. I'm working on RI5CY and s you can see in riscv_defines.sv, current mode holder is defined as:

// Privileged mode
typedef enum logic[1:0] {
PRIV_LVL_M = 2'b11,
PRIV_LVL_H = 2'b10,
PRIV_LVL_S = 2'b01,
PRIV_LVL_U = 2'b00
} PrivLvl_t;

And instantiated in riscv_core.sv

PrivLvl_t    current_priv_lvl;

Unfortunately I'm not aware on further documentation from the foundation. Hope this helps

user_31026380
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