Using don't-care in enumeration typedef in synthesizable SystemVerilog

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I have the following code:

typedef enum logic [1:0] {
  CMD1 = 2'b1?,
  CMD2 = 2'b01,
  CMD3 = 2'b00
} cmd_t;

Basically, if the MSB is 1, it's CMD1 (I'll use the LSB for part of the index). And if the MSB is 0, then decode the rest of bits for the command.

I then try to decode using an always_comb:

cmd_t myCmd;
always_comb begin
  casez(myCmd)
    CMD1: isCmd1 = 1'b1;
    CMD2: isCmd1 = 1'b0;
    default: isCmd1 = 1'b0;
  endcase
end

Unfortunately, I get this message from Spyglass:

[12EE]   W467 Based number 2'b1? contains a don't-care (?) - might lead to simulation/synthesis mismatch

This code should be synthesizable, no? Can this Spyglass warning be waived safely?

synthesis system-verilog
1 Answers

I doubt this will synthesise correctly. I think the Spyglass message is misleading. In Verilog (and SystemVerilog) ? means exactly the same as z. You are specifying an enum with 4-state base type values, where CMD1 is to be represented exactly by 2'b1z.

user_59000110
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