Can I capture simulator output to console in my testbench?

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I have a testbench to test my VHDL device (DUT), but part of the DUT debug output is an ASSERT/REPORT message to the console, which I would like to check for correctness but I can't change the DUT. The only way I can think of is to post-process the output log file.

Is there any way of capturing the console output in the testbench, so I can check the DUT output directly?

simulator vhdl unit-testing
1 Answers

I do this as part of the testbench. However, rather than Assert, I use OSVVM alerts, log, and print. OSVVM is both at osvvm.org and github.

Rather than Assert, I use AffirmIf for self-checking/result checking. I use AlertIf for parameter checking.

Step 1 is get OSVVM. Once you have the code, compile it using the script. In either Mentor or Aldec, run the script by doing:

vlib osvvm
vmap osvvm osvvm
do $PATH_TO_OSVVM/osvvm.do $PATH_TO_OSVVM

Use VHDL-2008 and include all of OSVVM in your program by doing:

library osvvm;
  context osvvm.OsvvmContext;

Then rather than:

assert Data /= expected report "..." severity error;

Do:

AffirmIf(Data = Expected, "...") ;

Both assert and AffirmIf/AlertIf print. However, the advantage to AffirmIf/AlertIf is that internally it keeps a count of the errors and you can get a pass fail at the end of your test by doing:

ReportAlerts;

The next advantage of OSVVM AffirmIf/AlertIf/Log/Print is that if you want the results in a file, you simply do:

TranscriptOpen("./results/Test1.txt");

If you want to both print to the screen and a file, also do:

SetTranscriptMirror(TRUE);

That ought get you started. I will leave the rest to the user guides. Start by looking at both the AlertLog package user guide and the transcript package user guide.

user_23679500
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