I've searched the documentation for Make and online forums. I've also searched the documentation for Bash. Maybe I've missed something.
I have a makefile containing
BUILD_SYSTEM :=$= build/make/core
BUILD_SYSTEM_COMMON :=$= build/make/common
include $(BUILD_SYSTEM_COMMON)/core.mk
What doe the $= mean?
You don't say what version of make you're using so I'll assume a standard POSIX-compliant version such as GNU make.
In makefiles, $x for any single character x means the expansion of a variable named x, with very few exceptions: $$ expands to a single $, $( and ${ indicate the start of a variable name. There may be a few other single characters that are special.
But other than those, any character can be a valid variable name. So $= expands to the value of the variable =, just like $a expands to the value of the variable a. This can be hard to set because simply using:
= = foo
won't work. But you can hide the equal sign from the make parser by using another variable:
EQUAL = =
$(EQUAL) = foo
all: ; @echo $=
then:
$ make
foo