Creating an array of child handles in system verilog

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In SystemVerilog, I have a base class A and derived class B, C, D. I would like to create an array of type A which has handles to B, C, D. Is there a more succinct way to do this then my ugly solution below?

module test; 
  A arr[3];
  B b;
  C c;
  D d;

  initial begin
    b = new();
    c = new();
    d = new();
    arr[0] = b;
    arr[1] = c;
    arr[2] = d;
  end
endmodule
system-verilog
1 Answers

If you mean without using the intermediate class variables, you can do 

arr[0] = B::new();

This is a relatively new feature of SystemVerilog and some tools do not support this yet. To get around this, you can create a static create method that calls the constructor for you, which lets you create a class object in places like an argument to a function without ever having to declare an intermediate variable.

class B;
  static function C create;
     create = new;
  endfunction
endclass

arr[1] = C::create();

somefunction(C::create()); // C::new() would not work here

If you are using the UVM library, you get this for free

class C extends uvm_object;
`uvm_object_utils(C)
...
endclass
arr[3] = C::type_id::create();
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