I'm trying to allow code running in non-root VMX mode to send IPIs from one core to another using an xAPIC. I'm implementing this functionality in both the VMM and the guest OS. I'm having difficulty getting this to work, and after spending hours reading through documentation, I wanted to reach out to see if anyone could point out any obvious flaws or help to consolidate some helpful info.
Here is my understanding:
In the EPT, I should map all guest physical address accesses to the memory-mapped APIC registers to the host physical base address of the memory-mapped APIC registers. Thus, when I try to write to the APIC registers in the guest OS, they will go to the APIC registers. To my understanding, since the CPU is in non-root VMX mode when this occurs, the APIC knows to virtualize these interrupts.
Next, when an IPI is received, a VM exit occurs with the exit reason EXIT_REASON_EXTERNAL_INTERRUPT. The VMM should then look through the ISR to find the bit set that corresponds to the received interrupt. Next, I inject the interrupt into the guest OS.
I think I'm sending IPIs correctly, or at least what I wrote above seems to be working properly. However, I'm having difficulty receiving IPIs. When I look through the ISR, no bit is set. Does anyone have any suggestions? I am using Intel Xeon CPU E5-2630, but I set the x2APIC to use the xAPIC interface by setting the nox2apic kernel parameter.