Chisel -- clock gating

user_2472001 0
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Clock gating is important for power reduction. How do we specify clock gating in Chisel?

Clock gating is where a logic signal determines whether or not the clock to a particular register is toggled. When the logic signal is inactive, then the clock remains steady, unchanging. Only when the enable is active does the clock signal toggle, which in turn latches inputs into the flip flop.

The backend tools handle inserting the implementation of this, but they need the RTL to indicate the enable signal.

riscv chisel
2 Answers

In my experience the backend tools do a good job of inferring clock gate enables (i.e. 95%+ of my registers in my Chisel SoC are clock gated).

Therefore I do not find myself needing to do what you ask, but if all you need is to specify the enable to a register this is easy with RegEnable.

user_18415280

Using Chisel3 MultiClock test as an example. I think this is pretty close to what you are looking for.

import chisel3._
import chisel3.experimental.withClock

class GatedCounter extends Module {
  val io = IO(new Bundle {
    val count = Output(UInt(32.W))
  })

  val counter = RegInit(0.U(32.W))

  counter := counter + 1.U

  io.count := counter
}

class HasGatedCounter extends Module {
  val io = IO(new Bundle {
    val enable = Input(Bool())
    val count  = Output(UInt(32.W))
  })

  val clock2 = (clock.asUInt()(0) & io.enable).asClock()

  withClock(clock2) {
    val counterModule = Module(new GatedCounter)

    io.count := counterModule.io.count
  }
}

Note: This does not seem to work with the firrtl-interpreter backend, so you must use the verilator backend or something else to test it properly.

user_3090390
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