Why does the makefile insist on compiling things it should not?

So I run make lex and it generates me the lex.yy.c file, all good

then I run make scanner, which takes a sourcefile called scanner.c into compilation, it should simply run cc lex.yy.c scanner.c -o scanner, but instead it does this:

lex  -t scanner.l > scanner.c
cc lex.yy.c scanner.c -o scanner 

Why does it decide to run lex -t scanner.l and output it to scanner.c effectively overwritting my code? No damned idea, and it's driving me crazy.

my makefile:

scanner: scanner.h scanner.c lex.yy.c
    cc lex.yy.c scanner.c -o scanner 

lex: scanner.l
    lex scanner.l > lex.yy.c

clean:
    rm lex.yy.c
    rm scanner

What's going wrong?