Conflict Miss v/s Compulsory Miss

user_5081701 0
Viewed 12821

Compulsory miss occurs when the block is brought first time into the cache.

Conflict miss in the case of set associative or direct mapped block placement strategies, conflict misses occur when several blocks are mapped to the same set.

Consider a 2 - way set associative cache memory with 4 sets and total 8 cache blocks (0 - 7) .Main memory has 64 blocks (0 - 63). If LRU policy is used for replacement and cache is initially empty then total number of conflict cache misses for the following sequence of memory block references is : 0 5 9 13 7 0 15 25

My doubt is, will 13 and 25 cause only compulsory miss or compulsory & conflict miss both?

cpu-architecture memory-management caching
2 Answers

Memory block references 0,5,9,13,7,0,15,25 In 2 way set associative cache memory with 4 sets - 0,5,9,13,7 will be compulsory misses. 0 hit. 15,25 will be compulsory misses. Any block accessed first time is always a compulsory miss. You can refer https://stackoverflow.com/a/40465392/6430403

user_103729860
Related