Makefile expanding variable inside define

define func1
    include $(shell pwd)/test/$(strip $1)/component.mk
    $(info :::::::${NAME} ::::::::::::::: )
endef

INCLUDES := a  b c

$(foreach dir, $(INCLUDES), $(eval $(call func1, $(dir)) ))

all : $(objs)

Contents of each makefile:

cat test/a/component.mk
    NAME := AA

cat test/b/component.mk
    NAME := BB

cat test/c/component.mk
    NAME := CC

Output is

::::::: ::::::::::::::: 
:::::::AA ::::::::::::::: 
:::::::BB ::::::::::::::: 

It looks like first time NAME is empty.