How to concatenate two arrays in VHDL

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I have some types like this :

Type MyCharacters is ('0', '1' ... '9', 'A', 'B', ... 'Z');

Type CharArray_8 is array(1 to 8) of MyCharacters;
Type CharArray_16 is array(1 to 16) of MyCharacters;
Type CharArray_32 is array(1 to 32) of MyCharacters;

and 4 Signals with this types :

Signal S1, S2 : CharArray_8;
Signal S3 : CharArray_16;
Signal S : CharArray_32;

I want to concatinate S1, S2 and S3 and assign the result to S, like this :

S <= S1 & S2 & S3;

but this code is wrong and have error, how I should concatenate them ?

Should Array types be declared as SubType of MyCharacters ?

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