I have a recent 12 core Intel CPU (Haswell architecture) and it has 4 memory channels. How many DRAM memory accesses can the machine do in parallel?
For example, if I have a program that uses 12 threads that sit in a tight loop that reads a single byte from random memory addresses over a range too large to fit in cache. I expect all 12 threads will spend almost all of their time waiting for the memory fetch.
Do the threads have to take it in turns to use the DRAM bus?
NOTE: Assume I'm using a 1-GB VM page size so there are no TLB cache misses.