I want to have an elegant way of adding a logic analyzer to an entity (chipscope for xilinx fpgas). Like described in ug936 there is the possibility to add an attribute to a signal (can be seen on page 10). This tells Vivado to keep the signal names (more or less) so that I can add them to the logic analyzer core. The described method has the drawback that I need to do this by hand for every signal I want to trace. Which makes this method very error prone.
Is there any possibility in vhdl to get all declared signals within an entity and to iterate over it and assign the attribute in a loop?